Job Description:

**Job Id** E1960814

**Job Title** Circuit Design Engineer

**Post Date** 11/28/2017

**Company-Division** Qualcomm Datacenter Technologies, Inc.

Qualcomm Datacenter Technologies, Inc.

**Job Area** Engineering – Hardware

**Location** North Carolina – Raleigh

**Job Overview** Work with Qualcomms DCG Server SOC Chip Clock team, to implement high frequency, low power dissipation, low skew global clock distributions. Main duties include:

1.Help support a custom clock tree timing and simulation methodology 2.Work closely with the Physical design clock team members to consult on all aspects of custom clock tree design and implementation, including the following: a. Run Spice simulations and write and support Spice based scripts that assist PD designers in early design of custom clock trees b.Validate custom clock cell design, extraction correlation, IR drop, or other custom circuit issues requiring careful layout and extraction based analysis c. Time clock distribution and support clock distribution skew reduction efforts. Collect characterization data and correlate silicon measurements to Spice model

3. Evaluate stdcell clock components for high frequency operation.

4. Design clock distribution circuits to meet high frequency requirements. Work with PD team to implement clock distribution.

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

**Minimum Qualifications** BSEE and 3+ years direct experience in the following:

-Custom circuit design experience, including schematic capture, Spice simulation, and familiarity with custom layout tools such as Virtuoso.

-Working knowledge of 14 nm and below technology transistor device characteristics, device modeling, understanding of layout effects on device electrical parameters, and mitigation strategies in layout implementations

-Experience writing PERL, Tcl (or other language) scripts to automate a variety of design tasks relating to custom clock design and large volume data handling

-Exposure to industry standard PD (Physical Design, place and route, DRC validation, EM, IR) tool and flows for 14 nm and below technologies, including a good understanding of Static timing analysis (Primetime or similar)

**Preferred Qualifications** MSEE preferred Working knowledge of layout parasitic extraction tools.

**Education Requirements** Required: Bachelor’s, Electrical Engineering

**EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.**

About Qualcomm

Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.