Job Description:

**Job Id**


Job Title

Design Optimization Engineer (Staff or above)

Post Date



Qualcomm Technologies, Inc. at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering – Hardware


California – San Diego

Job Overview

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.

The DTECH group is a part of the Global SOC organization, which designs SOCs for our mobile, compute, and automotive platforms. DTECH is responsible for innovation in methodology for design implementation and analysis, as well as timing signoff, thermal signoff, low power design, technology evaluation, and test chip design. DTECH also has significant contributions in design of digital process monitors and root causing and resolving design related issues on product silicon.

Primary Job Responsibilities:

+ Design Interface to Silicon Teams

+ Track design related yield issues

+ Root cause yield issues from the design side

+ Develop new methodologies to understand and prevent yield failures on future products and revisions

+ Understand and analyze silicon data including diagnostics data and process monitor data

+ Work with silicon test engineering teams, process technology teams, design teams, and methodology teams to gather data, analyze, and effect changes to design

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications

+ Bachelor’s degree in Science, Engineering, or related field.

+ 5+ years ASIC design, verification, or related work experience.

Preferred Qualifications

+ Good understanding of transistor-level digital design

+ Prefer exposure to automated place and route flows as well

+ Understanding of static timing analysis and timing methodology

+ HSPICE and PTSI simulation

+ Automation using Perl, Python, TCL, etc.

+ Prefer a basic understanding of silicon processing and silicon test engineering

+ Ability to work and collaborate with varied teams, such as methodology, physical design, circuit design, process technology and test engineering

+ Innovative with broad knowledge of design and methodology

+ Excellent problem solving and analysis skills are a must

+ Excellent written and verbal communication and presentation skills.

+ 8+ years ASIC design, verification, or related work experience.

+ MS in Electrical Engineering or higher preferred with 5-10 years experience

Education Requirements

Required: Bachelor’s degree in CE, CS, or EE.

Preferred: Master’s degree in CE, CS, or EE.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

About Qualcomm

Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.