Job Description:

**Job Id** T1960461

**Job Title** Design Verification (DV) Engineers – (San Diego, CA)

**Company-Division** Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

**Job Area** Engineering – Hardware

**Location** California – San Diego

**Overview** Qualcomm uses a centralized recruiting process designed to allow applicants to be reviewed by multiple hiring managers and departments by applying to a single posting. If you have experience in functional or formal design verification, you should apply to this posting. Qualcomm’s Design Verification Team has multiple positions available in San Diego, CA. This team is responsible for developing design corresponding test plans, architecting and developing verification environments, verification of complex designs until coverage goals are achieved dynamically or statically, and completing all required verification activities at IP, sub-system, SoC, and system/architecture level to insure high quality commercial success of our products. These positions range from entry-level to Principal/Director, although most do not include functional management responsibilities. The technical disciplines, languages and methodologies included in this team are:

+ **SOC Design Verification** (ARM, AMBA, AHB, AXI, Peripherals, clock, security)

+ **Modem Design Verification** (LTE, WCDMA, UMTS, CDMA,DSP)

+ **Multimedia Design Verification** (Graphics – OpenGL/CL, DX-9/10/11, Video codec – h.263/4/5, MPEG-2/4, VC1, VP6/7/8, Imaging – MIPI-CSI, ISP, JPEG)

+ **PHY Design Verification** (Analog/Mixed-Signal, High-Speed, SerDes, IO, D-PHY, M-PHY, USB2.0, USB3.0, HDMI, SATA, Verilog_AMS, VerilogA, SystemVerilog, VERA, Behavior Modeling, FPGA, Empulation, Spice Simulation)

+ **Formal Design Verification** (Jasper, 0-in, IFV, OneSpin, SLEC, Model Checking)

+ **Low-Power Design Verification** (UPF, CPF, Power Artist, AVS)

+ **Verification Design Automation** (EDA tools, Simulation Acceleration, Hardware Emulation: EVE, Cadence Palladium, Mentor Veloce, Synopsys HAPS, FPGA/ASIC-based emulator)

**Minimum Qualifications:**

+ 2+ years of industry experience in a Design Verification role.

+ Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC.

+ Hardware description languages (HDL) such as Verilog, SystemVerilog and VHDL.

+ Analytic and debugging skills.

+ Strong knowledge of digital design.

+ Understanding of Object Oriented Programming (OOP) concepts.

+ C/C++, Perl, Tcl, Java Programming.

**Education Requirements** Required: Bachelor’s, Computer Engineering and/or Computer Science and/or Electrical Engineering

Preferred: Master’s, Computer Engineering and/or Computer Science and/or Electrical Engineering



**EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.**

About Qualcomm

Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.