**Job Id** E1956639
**Job Title** DFT Engineer
**Post Date** 06/27/2017
**Company-Division** Qualcomm Datacenter Technologies, Inc.
Qualcomm Datacenter Technologies, Inc.
**Job Area** Engineering – Hardware
Engineering – Server
**Location** North Carolina – Raleigh
California – San Jose
**Job Overview** Candidate will be responsible for DFT architecture and test methodology definition, and driving implementation, primarily for Scan-based (ATPG) testing of high-end SoCs. The candidate will perform a technical leadership and innovation role within a team of 10-15 DFT design and ATPG engineers and programmers, to define DFT structures and tool flows needed for testing next-generation high-end server SoC products, and drive their successful implementation. In addition to work within a DFT team, the candidate will work with hardware design teams to ensure successful implementation of various DFT structures in RTL, and with SoC implementation teams including synthesis, physical design, clocking, timing, as well as design verification. The candidate will also work with Product and Test Engineering (PTE) teams to drive successful bring-up of test vectors on ATE platforms. This role will span current as well as future SoC products, and as such the candidates activity will span strategy, design, methodology, and test execution. The candidate will interface with internal tool development teams and will be responsible for driving synergies that facilitate test insertion, clock design, and vector development automation. Finally, the candidate will work with tool vendors, such as Mentor Graphics and Synopsys, to define and integrate tool capabilities (particularly DFT insertion and ATPG) needed to implement and roll out DFT strategies.
Test strategy definition
DFT Architecture for large multi-core server chips
Logic specification and RTL design of DFT IP
DFT team leadership of related activities
ATPG test planning, including coverage, test time, test memory footprint on ATE
Coordinate cross-functional front-to-back SoC implementation and verification of DFT structures
Bring-up of ATPG patterns on ATE
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
**Minimum Qualifications** – 15 years of experience are required in the following areas:
– Defining and executing DFT-related tool flows, spanning insertion, ATPG, as well as DFT requirements in front-to-back SoC implementation flows
– Test vector planning for bring-up and production, and hand-on ATE bring-up experience
– Achieving high coverage via SAF, TDF, as well as knowledge of other techniques such as Small Delay Defects, Path testing, LOC/LOS, etc.
– Tessent, DFTC, TCL/PERL, IEEE 1149 and 1687, Primetime, SpyGlass, Verilog simulation including SDF, Advantest ATE
– Architecting automation strategies that align with third party DFT tools and create further efficiencies
**Preferred Qualifications** – Experience leading large DFT/ATPG teams and defining/bring-up of DFT architecture, including hierarchical core/chip based flows and pattern retargeting
– Experience with large device test on ATE and with architecting DFT strategies in support of multi-core and parallel testing
**Education Requirements** Required: Bachelor’s, Electrical Engineering
**EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.**
Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.