Digital ASIC Design Engineers (San Diego, CA and Bay Area)
Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
Engineering – Hardware
California – San Diego
Qualcomm’s Digital ASIC Design team has multiple positions available. This team is responsible for the entire digital design flow from RTL to GDSII, including digital and mixed-signal circuits and systems that are integrated into integrated circuits (ICs), System-on-Chip (SoC) and complete chipsets that power Qualcomm’s wireless device portfolio. The team is currently seeking candidates across a broad range of technical areas. These positions range from entry-level to Principal, and are available in San Diego, CA.
3+ years of industry experience in the following areas:
+ ASIC frontend development.
+ Logic design, RTL coding, verification, synthesis, and timing closure.
+ Hardware description languages (Verilog, System Verilog and VHDL).
+ AMBA bus standards such as AXI, AHB, and ACE
+ Synopsys DC/PrimeTime or similar tools.
+ Scripting/programming in C/C++, Tcl, Perl/Csh. **Preferred Qualifications:** 3+ years of industry experience in 1 or more of the following technical disciplines:
+ **SoC Design** (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI)
+ **RTL Design** (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency)
+ **Low Power Design** (clock gating, power gating, power grids, Power Artist, UPF, CPF)
+ **High-Speed DDR Controller** (Memory Controller, CPU, SRAM & L3 Cache, x86 or ARM CPU/bus architecture)
+ **Audio Codec ASIC Hardware** (Audio DSP Implementation, Audio Algorithm, Low-Power Voice/Audio Activation, Noise Cancellation)
+ **Graphic ASIC Hardware** (GPU or CPU cores, DX9/10/11 level graphics HW development)
+ **Multimedia/Camera Imaging/Video** (Image processing algorithms, ASIC Design, RTL Coding, JPEG, C/C++/SystemC, Modelsim, Synopsys DC, LEC, Spyglass)
+ **Physical Layer Design** (PHY, USB, HDMI, DDR, MIPI)
+ **SerDes Application** (PHY Layer Protocol, SerDes PHY, ASIC EDA Models, Cadence Schematics)
+ **Digital Design for Mixed Signal ASICs** (PLL, Phase-Lock-Loop, LNA, OpAmp, ADC-DAC)
Required: Bachelor’s in Computer Science, Computer Engineering, and/or Electrical Engineering.
Preferred: Master’s or PhD in Computer Science, Computer Engineering, and/or Electrical Engineering.
EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.
Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.