Implementation Engineer – Santa Clara
Qualcomm Technologies, Inc. at http://www.qualcomm.com/about/businesses/qct
Engineering – Hardware
California – Santa Clara
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.
Candidate will be responsible for developing next wireless Modem cores for enterprise, mobile and adjacent market applications. This role will require the candidate to understand and work on synthesis, logic equivalence, constraints generation, timing closure, low power verification, full chip physical aware and power aware synthesis, static timing analysis, constraints validation and , IO timing closure. This candidate will take RTL delivery and own and deliver one or more design blocks/tiles and deliver DFT inserted netlists to physical design team. This candidate will work closely with front end design and physical design teams to close timing in sub-micron technologies (from 14nm to 7nm and below). The candidate may also work on power simulations , multi-voltage, and low power synthesis flows. The candidate should have extensive knowledge in constraints and be able to work on netlist level ECOs manually or with conformal ECO with little guidance. The candidate should also possess automation skills and be well versed in scripting languages. The candidate may also be required to mentor junior members of the team.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
+ Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field.
+ Masters in Electrical Engineering
+ Design quality [LINT, CDC, testability, low-power] checks.
+ Memory-bist, DFT insertion, standard-cell-based synthesis and logic equivalence checks.
+ DFT checks as well as advanced design-constraint-checks.
+ Vector-based and vector-less power-analysis – Floor-planning, timing analysis and timing closure.
+ Experience in ASIC synthesis, timing closure, formal verification, low power verification.
+ Working knowledge of industry leading synthesis tool and static timing analysis tools.
+ Good understanding of timing constraints development.
+ Good understanding low power and power simulations using ptpx/power artist/conformal low power.
+ Debugging knowledge of physical aware and power aware synthesis.
+ Sound engineering practices in breaking down a problem into its components and solving it.
+ Good analytical ability, problem solving skills and be a self-starter.
+ Candidate should be able to lead and work in a team environment.
+ Good understanding logic equivalence using industry standard tools like conformal, conformal low power.
+ Good understanding of System Verilog.
+ Good understanding of DFT methodologies, memory BIST flows.
+ Knowledge of Conformal ECO.
Required: Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field
Preferred: Masters in Electrical Engineering
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.