NoC interconnect Architect and Design Engineer
Qualcomm Technologies, Inc. at http://www.qualcomm.com/about/businesses/qct
Engineering – Hardware
California – San Diego
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.
QCT GSoC team is looking for bright engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast-paced team responsible for defining and delivering SoC interconnects.
Successful candidate will be part of be a multi-disciplinary SoC interconnect team involved from early product specification to final RTL delivery to the SoCs.
Candidates should have strong knowledge of bus protocols, debug infrastructure, and synthesis tools including successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.
Candidate will be responsible for:
+ Creation of architecture bus components specifications as well as delivering RTL and running tool flows.
+ Identifying architecture bottlenecks and driving architecture choices to provide the team with design guidelines for bus protocol compliance and optimal interconnect.
+ Regular meetings with SoC/SW/debug/Post silicon and IP teams to define and execute new and updated interconnect architectures.
+ Responsibilities also include evaluating new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC.
+ Candidate should also be able to deliver RTL, support verification and silicon validation teams, and work with debug and SW teams to support successful deployments of the interconnects.
+ Support verification and post silicon validation teams in debugging any issues and enable any new debug features by providing configuration info and documentation, as well as supporting all teams during bring-up activities
+ Address synthesis, placement and routing congestion and timing closure challenges
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
+ Bachelor’s degree in Science, Engineering, or related field.
1+ yrs experience with solid knowledge of NoC interconnect design including architecture, verification of integrated systems, RTL design, debug, synthesis, and timing closure.
+ Strong knowledge of ASIC flow (synthesis, STA, Lint), debug and power tools.
+ Strong Knowledge of various bus protocols (AHB, AXI, ACE, ) and network on chip.
+ Strong problem solving to interpret performance analysis and make design tradeoffs.
+ Strong working knowledge of architecture tradeoff analysis and debug IPs.
+ Ability to define bus components micro-architecture while taking into account performance/power/area tradeoff.
+ Ability to quickly react and adapt to changes.
+ Excellent communication skills.
+ Familiarity with debug infrastructure and CPU architecture is a big plus.
Extensive RTL experience required. Power and Verification experience is a bug plus.
EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.