**Job Id** E1958294
**Job Title** Physical Design Engineer (Santa Clara, CA)
**Post Date** 10/25/2017
**Company-Division** Qualcomm Technologies, Inc.
CDMA Technology at http://www.qualcomm.com/about/businesses/qct
**Job Area** Engineering – Hardware
**Location** California – Santa Clara
**Job Overview** Qualcomm’s Embedded Digital Physical Design Team is responsible for the drive and execution of all phases of the complete netlist-to-GDSII flow for all embedded digital circuits in Analog IP. Design scope ranges from block-level to chip-level across many QC product lines, including modem, transceiver, power management, and RF front-end. We are actively seeking candidates for multiple Physical Design positions in San Diego, CA. **Responsibilities:** You will be part of a team responsible for the complete Physical Design Flow for embedded digital circuits. Tasks involved can be one or more of the following:
+ Work with the design team on understanding in context of physical timing closure, including development of timing constraints required for implementation and signoff.
+ Lead block- and chip-level signoff closure activities, including timing, physical verification, powergrid verification, logical equivalence, and power domain integrity .
+ Develop new scripts/flows to improve implementation and closure processes.
+ Complete netlist-to-GDSII implementation of embedded digital circuits.
+ Implement and develop low-power implementation methods, including use of headswitches, clock gating, multi-vdd, and multi-vth
+ Block- and chip-level floorplanning, powergrid, placement, CTS, P&R, PV, timing, and Signal Integrity Analysis.
+ Work closely with analog design teams to implement highly-customized PNR solutions.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
**Minimum Qualifications** **Bachelor’s degree and 3+ years experience in 4 or more of the following areas:**
+ Physical implementation (Floorplanning, CTS, STA) for CPUs and GPUs in advanced technologies
+ STA tool and closure methodologies, including experience with MMMC and rapidly-advancing STA inputs
+ Power grid, clock tree, and low-power reduction implementation methods
+ Signal integrity and timing closure methodologies such as OCV/AOCV/Statistical
+ Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification
+ Programming and scripting skills (Tcl, perl and/or C)
**Preferred Qualifications** **Additional experience/skills considered a plus:**
+ Master’s degree
+ Power-aware yield estimation
+ Vmin optimization
+ Power recovery
+ Semi-custom of structured blocks
+ Clock tree analysis and optimization
+ Strong verbal and written communication skills
**Education Requirements** Required: Bachelor’s, Computer Engineering and/or Computer Science and/or Electrical Engineering
Preferred: Master’s, Computer Engineering and/or Computer Science and/or Electrical Engineering
**EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.**
Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.