**Job Id** E1957794
**Job Title** Principal Design Engineer – QDT Server Path-Finding Group
**Post Date** 08/10/2017
**Company-Division** Qualcomm Datacenter Technologies, Inc.
Qualcomm Datacenter Technologies, Inc.
**Job Area** Engineering – Hardware
Engineering – Server
**Location** California – San Jose
California – San Diego
North Carolina – Raleigh
**Job Overview** Research and Path-finding on very high-performance, low power, reliable Die-to-Die Interface technologies for Dense Multi-Chip Modules.
Identify and analyze alternatives and then drive selection and specification process
Includes researching literature and industry for competing alternatives, analyzing circuit design approaches, dynamic equalization techniques, SI and timing studies, clocking schemes, power and die area analysis, power supply requirements, reliability analysis, error recovery mechanisms, and performance modeling.
Develop the IO architecture that integrates the Die-to-Die interface technology into the multi-chip SoC. This includes, defining clocking architecture and clock domain synchronization, dynamic techniques for error recovery and power management, power supply requirements including voltage regulation needs.
Design and deliver test chip and perform lab measurements and characterization work on main alternatives to assist in selection process.
Mentor and guide junior engineers on various aspects of analysis, design and debug, validation, and testing.
Drive technology transfer from path-finding to product development.
All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.
**Minimum Qualifications** At least 7 years of experience are required in following areas:
– IO designs, familiarity with state-of-the-art techniques for very high-speed interfaces, low power design techniques, SI analysis and clocking architectures including PLL/DLL design.
– Mixed-signal and CMOS design techniques.
– Designing with 10nm and sub-10nm CMOS process nodes is a plus.
– Experience with best design practices to minimize device mismatch, noise, and signal coupling.
– Knowledge of semiconductor processes and device physics related to CMOS silicon technologies.
– Experienced in chip top level integration, pin out and package selection.
– Understanding of transistor simulation models, design rules and verification procedures (DRC/LVS/ERC).
– Proficiency in the use of various existing CAD tools to assist in analysis and development is required.
**Preferred Qualifications** – Self-motivated with the ability to work in a research and path-finding environment where requirements and scope can be ambiguous or changing.
– Proven ability in oral and written presentations to technical peers and senior management.
– PhD in Electrical Engineering with a minimum of 5 years for direct research or industry experience in circuit design, I/O interfaces, SerDes design, clocking architectures.
– A track record of innovation in high-speed interfaces and low power design techniques is a plus.
– Experienced in designing various analog/mixed-signal blocks for IO circuits: DFEs, filters, DLLs PLLs, voltage references, buffers, etc.
**Education Requirements** Required: Master’s, Electrical Engineering
Preferred: Doctorate, Electrical Engineering
**EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.**
Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.