Senior or Staff IC Packaging Engineer – Mechanical Simulation

Overview

Job Description:

**Job Id**

E1981494

Job Title

Senior or Staff IC Packaging Engineer – Mechanical Simulation

Post Date

05/01/2020

Company

Qualcomm Technologies, Inc. at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering – Hardware

Location

California – San Diego

Job Overview

This position is part of Qualcomms Integrated Circuits (IC) packaging team. This role offers an opportunity to impact Qualcomm’s current/future chipsets using FEA expertise, working closely with new product introduction (NPI) and Chip-Package Interaction (CPI) teams by providing mechanical simulation support for current HVM and advanced packaging technologies. This role requires development of mechanical FEA models (preferably using ANSYS APDL), develop and maintain APDL macros/workflows, establish FEA methodology for test correlation, material characterization, perform stress/mechanical analysis for IC package designs and failure prediction. Job responsibilities include but not limited to: Warpage, Stress analysis, Solder joint reliability (SJR) analysis, package assembly process simulation, and chip-package-board interaction. The candidate must be capable of using advanced Finite Element Analysis (FEA) techniques (such as sub-modeling approach, contact analysis, and non-linear analysis), and test equipment for material characterization/testing. Candidate should also understand the concepts of device, package and board level interconnect technologies. The candidate is expected to have strong communications, project definition and execution skills.

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications

+ Masters degree in Mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.

+ 3+ years of hardware engineering experience and related work experience in FEA analysis and IC electronic packaging

Preferred Qualifications

+ 5+ years of combined experience in Finite Element modeling and Analysis for IC electronic package and interconnects.

+ 2+ years of experience in ANSYS (APDL preferred)

+ v3+ years of work experience in Semiconductor and IC microelectronic packaging industry

+ 3+ years of experience in the fundamentals of IC electronic packaging structures and assembly processes, reliability testing and analysis, Chip-Package Interaction, Package-Board interaction and design of experiments (DOE).

+ Solid understanding of packaging materials and their mechanical behaviors. FEA experience in Flip chip/FCBGA packages, understanding of TIM/lid adhesive behavior and its predictions would be considered a plus.

+ 2+ years of experience in material testing for strength and fracture with experience in designing and executing mechanical test methods (plus)Research and publications in FEA predictive modeling, Warpage/SJR work, and/or interfacial fracture testing (plus).Good analytical and project management skills.Excellent communications and presentation skills.Self-starter, highly motivated and committed to product success.Able to work flexible hours. Occasional domestic/international travels may be needed

Education Requirements

Required: Master’s, Electrical Engineering and/or Materials Science and/or Mechanical Engineering

Preferred: Doctorate, Electrical Engineering and/or Materials Science and/or Mechanical Engineering

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.