Overview

Job Description:

**Job Id** E1959744

**Job Title** Senior Physical Design Engineer – RF Front-End (RFFE)

**Post Date** 11/29/2017

**Company-Division** Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

**Job Area** Engineering – Hardware

**Location** California – San Diego

**Job Overview** Qualcomm’s Digital Physical Design Team is responsible for the drive and execution of all phases of the complete netlist-to-GDSII flow for all embedded digital circuits in Analog IP. Design scope ranges from block-level to chip-level across many QC product lines, including modem, transceiver, power management, and RF front-end. Responsibilities: You will be part of a team responsible for the complete Physical Design Flow for embedded digital circuits. Tasks involved can be one or more of the following:

Work with the design team on understanding in context of physical timing closure, including development of timing constraints required for implementation and signoff.

Lead block- and chip-level signoff closure activities, including timing, physical verification, powergrid verification, logical equivalence, and power domain integrity .

Develop new scripts/flows to improve implementation and closure processes.

Complete netlist-to-GDSII implementation of embedded digital circuits.

Implement and develop low-power implementation methods, including use of headswitches, clock gating, multi-vdd, and multi-vth

Block- and chip-level floorplanning, powergrid, placement, CTS, P&R, PV, timing, and Signal Integrity Analysis.

Work closely with analog design teams to implement highly-customized PNR solutions.

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

**Minimum Qualifications** At least 5 years experience in 4 of the areas below:

Physical implementation (Floorplanning, CTS, STA) in advanced technologies

STA tool and closure methodologies, including experience with Primetime and rapidly-advancing STA inputs

Power grid, clock tree, and low-power reduction implementation methods

Signal integrity and timing closure methodologies such as OCV/AOCV/Statistical

Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification

Programming and scripting skills (Tcl, perl and/or C)

**Preferred Qualifications** Power-aware yield estimation

Vmin optimization

Semi-custom of structured blocks

Clock tree analysis and optimization

Strong verbal and written communication skills

**Education Requirements** Required: Bachelor’s, Computer Engineering and/or Electrical Engineering

Preferred: Master’s, Computer Engineering and/or Electrical Engineering

**EEO employer: including race, gender, gender identity, sexual orientation, disability & veterans status.**

About Qualcomm

Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.