Overview

Job Description:

**Job Id**

E1981038

Job Title

Timing Methodology Development and Automation Engineer

Post Date

05/19/2020

Company

Qualcomm Technologies, Inc. at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering – Hardware

Location

California – San Diego

Job Overview

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.

The candidate will be responsible to work in the area of Timing Methodology and Physical Design flows development to be used for complex VLSI SOCs implementation and sign off across multiple technology nodes from 28nm to 3nm. Responsible for in-house Tool/Applications development and commercial EDA timing tools and flows validation. Individual contributor for automation, data generation and analysis, massive STA and spice simulations and digital physical design implementation and/or verification flows (including 3D).

**Key qualifications (Expertise in any 2 of the following areas):** The candidate will be responsible to work in the area of Timing Methodology and Physical Design flows development to be used for complex VLSI SOCs implementation and sign off across multiple technology nodes from 28nm to 3nm. Responsible for in-house Tool/Applications development and commercial EDA timing tools and flows validation. Individual contributor for automation, data generation and analysis, massive STA and spice simulations and digital physical design implementation and/or verification flows (including 3D).

Key qualifications (Expertise in any 2 of the following areas):

1.Hands on experience with Static Timing Analysis using Primetime and/or Tempus including Timing convergence, Timing ECO, Timing sign off for IP/HM/Subsystem/SOC flat or hierarchical. Timing sign off flow automation and support, Timing constraints generation and validation.

2.Experience with Timing/Power corners, STA vs. Spice correlation, PVT corners, Standard Cell Library modeling and characterization, Monte Carlo simulation, High Sigma Monte Carlo analysis, Process technology modeling and characterization, Process variation modeling

3.Experience in design automation using TCL/Perl/Python, C/C++, Matlab, Unix shell scripting, EDA tools flow automation, Database management, Load balancing tools (LSF), CAD support

4.Experience with Liberty Library modeling NLDM/CCS/CCSN/ECSM and library variation using CBAOCV/POCV/LVF/Moments. On chip variation AOCV/POCV. Library accuracy validation. UPF/UPF2.0 library modeling requirements.

5.Familiar with VLSI digital flow design implementation RTL to GDS : Synthesis: DC/DCT/DCG, Genus, P&R: ICC, Innovus , STA Timing: PT/Tempus , Parasitic Extraction: StarRCXT, Quantus, Calibre ,Raphael , Physical ECO: Tempus ECO, PT ECO, Dorado, PG sign off: RedHawk, Voltus, Physical verification: DRC/LVS/ERC Calibre, PERC, Formal verification: LEC, CLP, Spyglass, Leakage recovery flows, Power recovery flows, High Performance Clock tree implementation and validation/verification including Duty Cycle Distortion (DCD) and Rail to Rail (R2R) failures sign off. , DFM

6.Familiar with process technology enablement: Technology files definition for physical design tools. PDK enablement, PPA analysis, Spice simulation Hspice/FineSim/Spectre/AFS, Monte Carlo. Process technology evaluation device FEOL and MOL/BEOL parameters (Planar, FinFET technology, SOI, Nano sheets/Nanowire). Reliability assessment FEOL/BEOL. Silicon to spice model correlation, aging models OMI/TMI validation and usage for circuit design analysis and optimization

7.Computer science or/and Electrical engineering background. Linear programming, statistical analysis and Machine Learning.

8.Good communication skills. Able to work independently and in a team. Good presentation skills. Open to innovation and new technological challenges

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company.

Minimum Qualifications

+ Bachelor’s degree in Science, Engineering, or related field.

+ 2+ years ASIC design, verification, or related work experience

Preferred Qualifications

+ MS and/or PhD

+ High level of experience with Timing sign off, Design/Timing Methodology Development, Design Automation, SOC tapeout flow, plus experience in the following areas:

+ Timing Sign off., Timing ECO, VLSI Physical Design, Timing Methodology

+ Library modeling, Spice simulation, Library characterization

+ Automation in TCL/Perl/Python , C/C++., Machine Learning model generation, training and validation

+ RTL to GDS physical design implementation flow, SOC tapeout flow

Education Requirements

Required: Bachelor’s

Preferred: Master’s and/or PhD

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

About Qualcomm

Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.