Company:Qualcomm Technologies, Inc.
Job Area:Engineering Group, Engineering Group > GPU ASICS Engineering
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.
Qualcomm CDMA Technologies is the world leader in wireless ICs powering the majority of 3G, 4G and the newest 5G devices as well as being one of the largest fabless semiconductor company in the world.
The Graphics team is looking for an Engineer to work on Qualcomm’s Adreno Graphics cores in the area of implementation and methodology. The successful candidate will work in Adreno GPU team and will be responsible for various functions from RTL integration through to physical design.
As a member of the Graphics team, the successful applicant will help integrate, implement and develop state of the art GPU cores and will be working closely with the graphics microarchitecture and physical design teams. The successful candidate will possess in-depth understanding of ASIC design flow and the challenges posed by advanced deep sub-micron technologies. The Design Implementation Engineer will work in Qualcomm’s Adreno GPU team and will responsible for managing all aspect of front end implementation design challenges and methodology. The role will also include working with execution driven teams for tape-outs by supporting new methodologies and new flows required to address better QoR like performance, power and area. The responsibilities will include the following:
+ RTL to GDS2 flow, tools and methodologies such as synthesis, static timing analysis, formal verification, physical design and ECO generation/verification :
+ Implementation and delivery of GPU cores from RTL to GDSII
+ Identify areas for flow and process improvements
+ RTL synthesis using physically aware tools
+ Formal Verification using industry standard tools for RTL-netlist and netlist-netlist checks
+ Close design timing by running static timing analysis and constraint development
+ Generate and verify ECOs for functional and timing fixes, working closely with the physical design team
+ Low Power synthesis flows for multiple corners
+ Bachelor’s degree in Engineer, Science, or closely related field
+ 6+ months of experience with d igital design and RTL development
+ 6+ months of experience with synthesis, static timing, timing closure, constraints and formal verification
+ Knowledge and experience of graphics design and development
+ Proficient in Perl, TCL and shell scripting
+ Hands on experience with front end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality and Synopsys PrimeTime
+ Familiar with The latest EDA tools for synthesis, logic equivalence checking, timing Analysis, physical design
+ Able to problem solve complex, unique and detailed issues
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Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.