Company:Qualcomm Technologies, Inc.
Job Area:Engineering Group, Engineering Group > SoC Architecture
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.
As a Power Management Architect, you will work with chip architects to conceive of the system level macro-architecture and chip level micro-architecture of an efficient and high performance compute SoC. Your input will drive the product definition through early involvement in the product life-cycle.Role and ResponsibilitiesWork with chip architect to understand architecture concept and high level system requirementsDefine the control system that drives power state control and transitions (FSM and/or micro controller based)Define overall clocking scheme of major SOC blocks and chip interfacesParticipate in the definition of the boot up sequenceDefine the communication protocol between processor SOC and the PMICDefine power rails and power states for all major functional blocksDefine SOC level TDP power estimation and capping methodologyMust have good communication skills and able to work in dynamic environment with top level engineers and technologistsPreferred qualificationsMS degree in Electrical Engineering; 10 years of practical experienceKnowledge of SOC architectureFamiliarity with high performance and low power design techniquesKnowledge of major SOC interfaces like PCIE, DRAM, coherent socket to socket interfaces and PMIC to SOC links.Experience in power and performance telemetryExperience in TDP (thermal design power) capping and controlExperience in measurement and management of over-current and voltage droop events
Physical Requirements• Frequently transports and install equipment up to 5 lbs.• Performs required tasks at various heights (e.g. standing or sitting).• Monitors and utilizes computers and test equipment for more than 6 hours a day.• Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.
As a Power Management Architect, you will work with chip architects to conceive of the system level macro-architecture and chip level micro-architecture of an efficient and high performance compute SoC. Your input will drive the product definition through early involvement in the product life-cycle.
Role and Responsibilities
+ Work with chip architect to understand architecture concept and high level system requirements
+ Define the control system that drives power state control and transitions (FSM and/or micro controller based)
+ Define overall clocking scheme of major SOC blocks and chip interfaces
+ Participate in the definition of the boot up sequence
+ Define the communication protocol between processor SOC and the PMIC
+ Define power rails and power states for all major functional blocks
+ Define SOC level TDP power estimation and capping methodology
+ Must have good communication skills and able to work in dynamic environment with top level engineers and technologists
+ MS degree in Electrical Engineering; 10 years of practical experience
+ Knowledge of SOC architecture
+ Familiarity with high performance and low power design techniques
+ Knowledge of major SOC interfaces like PCIE, DRAM, coherent socket to socket interfaces and PMIC to SOC links.
+ Experience in power and performance telemetry
+ Experience in TDP (thermal design power) capping and control
+ Experience in measurement and management of over-current and voltage droop events
Bachelors – Computer Science, Bachelors – Electrical Engineering
2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands)., 8+ years Systems Engineering or related work experience.
Doctorate – Computer Science, Doctorate – Electrical Engineering, Masters – Computer Science, Masters – Electrical Engineering
8+ years experience with programming (e.g., C, C++, Python), computer architecture, or embedded systems. ,3+ years of work experience in a role requiring interaction with senior leadership (e.g., Vice President level and above) ,2+ years working with operating budgets and/or project financials ,4+ years in a technical leadership role with or without direct reports (only applies to positions with direct reports).
Caches, DSP Architectures, Machine Learning, Memory Management, Microprocessor Systems Design
Applicants: If you are an individual with a disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found here (https://qualcomm.service-now.com/hrpublic?id=hr_public_article_view&sysparm_article=KB0039028) for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. Qualcomm is an equal opportunity employer and supports workforce diversity.
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If you would like more information about this role, please contact Qualcomm Careers (http://www.qualcomm.com/contact/corporate) .
We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—we invent breakthrough technologies that transform how the world connects, computes, and communicates.
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Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.