Company:Qualcomm Atheros, Inc.
Job Area:Engineering Group, Engineering Group > Analog Mixed Signal Design
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age – and this is where you come in.
Oversees definition, design, verification, and documentation for development of a variety of CMOS mixed analog/digital blocks such as: data converters, PLLs, analog/digital filters, low drop out linear voltage regulators, precision references, comparators, fingerprint sensor AFE, audio amplifiers and high speed SERDES. Determines architecture design and circuit specifications based on system level requirements. Is actively involved in all aspects of the design from system definition/simulation to circuit design and simulation. Heavy involvement in overseeing layout and silicon evaluation is also expected. Uses design tools such as Cadence ADE, MathWorks MATLAB and others. Provides technical expertise for new initiatives (e.g., 5G, analog design automation).The responsibilities of this role include: · Working under some supervision. · Taking responsibility for own work and making decisions with limited impact; impact of decisions is readily apparent; errors made typically only impact timeline (i.e., require additional time to correct). · Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area. · Working within prescribed budget and resources. · Completing most tasks with multiple steps which can be performed in various orders; some planning and prioritization must occur to complete the tasks effectively; mistakes may result in some rework. · Exercising creativity to draft original documents, imagery, or work products within established guidelines. · Using deductive problem solving to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be required. · May be solicited during strategic planning period. The responsibilities of this role do not include: · Providing supervision/guidance to others. · Influence over key organizational decisions. Principal Duties and Responsibilities · Uses appropriate tools or databases to contribute to architecture and circuit designs for one or more blocks; participates in design reviews. · Works with layout teams to oversee block-level layout of one or more blocks. · Defines and runs own simulations and analyses (e.g., power, performance) on designs; documents and utilizes results to improve and verify designs. · Programs and runs tests to identify bugs in own work and helps more junior team members with the same; debugs most issues and escalates highly complex issues. · Consults with internal or external users as directed to assist with implementation and achieve goal alignment. · Maintains understanding of one’s technical domain and builds understanding of other domains to ensure integration with different components. · Writes detailed technical documentation and design descriptions to guide users and/or customers. · Collaborates with team members to generate ideas.
Looking for skilled ESD Design Engineer to support the product teams with ESD cell creation and ESD reviews.
+ Support product designers by design / development of ESD-robust I/O Libraries with I/O cells meeting product specific applications and environment.
+ Use Cadence Virtuoso to build DRC/LVS clean schematics and layouts of ESD Cells and I/O Cells in the new I/O Libraries which pass the ESD tests HBM, CDM and Device Level IEC61000-4-2.
+ Publish I/O Library Documentation and provide user guides for designers in the areas of EOS / ESD / EMI / RFI / Process Reliability and Latch-Up.
+ Perform ESD and Latch-Up Reviews of all products prior to tape out. Execute detailed analysis of ESD failures or Latch-Up failures including providing analysis of Final Test Data from failures.
+ Provide schematics and layouts of all product fixes which address ESD and Latch-Up failures.
+ Assist with failures in qualification tests in the areas of EOS / ESD / EMI / RFI / Process Reliability and Latch-Up.
+ Provide process support to all designers including handling process questions and providing local device physics support.
+ Provide support in all areas of new product qualification including HAST, Thermal Shock, HTOL, Temp-Cycle, etc. including analysis and providing fixes for failures in these tests.
+ Masters or higher in Electrical Engineering.
+ Experience in CMOS / BICMOS IC design, involving circuit simulation, with two years’ experience in ESD Cell and I/O Cell design, including Cadence Virtuoso Schematic and Layout creation, which address ESD / EOS / EMI / RFI issues.
+ Good documentation and communication skills and the ability to work independently and with others in a distributed environment with engineers in several locations.
+ Strong willingness to provide innovative circuit design solutions.
+ Applies knowledge and advanced analytical and/or technical interpretation to resolve a variety of complex problems.
+ Chip level floor planning and system level IC design experience highly desirable.
+ Use knowledge of EOS / EMI / RFI event simulation tools and techniques a plus.
+ Strong analytical skills.
+ Experience with Cadence or Mentor Graphics EDA tools.
+ Experience in the use of SPICE or Spectre simulation for circuit.
+ Excellent verbal and written communication skills.
+ Experience to use diverse laboratory tools for silicon evaluation.
+ Knowledge of Verilog and/or AMS modeling for mixed-signal verification.
+ Experience with Linux workstation environment.
Physical Requirements · Frequently transports between offices, buildings, and campuses up to ½ mile. · Performs required tasks at various heights (e.g., standing or sitting). · Monitors and utilizes computers and test equipment for more than 6 hours a day.· Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.
Masters – Electronic Engineering, See the required degree associated with years of work experience
2+ years ASIC design, verification, or related work experience., 2+ years experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET:, 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).
Doctorate – Electrical Engineering
2+ years experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., VCO, PLL, and DLL design, Audio CODEC and Class D Audio amplifier design, Delta-Sigma, SAR ADCs, Current-Steering DACs, high speed DDR PHYs, high-speed SERDES).
Analog Circuits Design, Analog Integrated Circuits, Cadence Skill, Data converter, Matlab C
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Who is Qualcomm, and what do we do? We are engineers, scientists and business strategists. We are from many different countries and speak many different languages. We come from diverse cultures and have unique perspectives. Together, we focus on a single goal—invent mobile technology breakthroughs.